Use of Hierarchy in Fault Collapsing

We discuss the advantage of using hierarchy in testing. Our demonstration is based on the problem of fault collapsing. Though this problem is not considered to be too complex, the time of collapsing faults in moderately large circuits can be several hours or more. This can be considerably shortened by hierarchical fault collapsing. Large circuits are efficiently described using hierarchy, which significantly helps the architectural design, verification and physical design. In hierarchical collapsing, we do not flatten the circuit and the collapsed fault sets computed once for subcircuits are reused for all instances of those sub-circuits. The time required for collapsing a flattened 8192-bit ripple carry adder using a test program like Hitec is 84 minutes, while the fault collapsing using multiple levels of hierarchy takes 55 seconds. When functional functional fault techniques are used for smaller sub-circuits, hierarchical fault collapsing results in collapse ratios lower than those obtained with structural collapsing of flattened circuits, without compromising on the reduction in the CPU time for collapsing. Using functional collapsing for a full adder library cell, we hierarchically collapse faults in a 8192-bit adder to sets of 196,610 equivalence and 98,304 dominance collapsed faults. In comparison, the flattened circuit collapses into 294,914 and 229,378 equivalence and dominance collapsed sets, respectively. The advantage of smaller collapse ratios may be in the reduction of fault simulation effort and in the number of test vectors. It has been observed that the CPU time for structural fault collapsing for Boolean circuit by conventional programs grows as the square of the circuit size. A closer to linear time complexity can be expected for hierarchical fault collapsing.